1. Technical Field
The present application relates generally to an improved integrated circuit device package. More specifically, the present application is directed to an electrically optimized and structurally protected via structure for high speed signals in multilayer interconnection substrates, such as printed circuit boards, multilayer ceramic packages, and multilayer organic packages.
2. Description of Related Art
Current multilayer interconnection substrates, such as multilayer organic packages or multilayer ceramic packages, and printed circuit board (PCB) constructions require one or more external conductive layers, e.g., circuitry and/or pads for mounting components thereon, and, given today's increased functional demands, a plurality of internal conductive planes, e.g., signal, power and/or ground. To provide effective interconnections between components and the multilayer interconnection substrate's conductive circuitry and pads, the use of through holes has been adopted wherein several such holes are passed through the multilayer interconnection substrate and electrically coupled in a selective manner to internal and external conductive elements. Such holes typically include a conductor, such as copper, which may fill or at least layer the hole. The conductor in turn contacts circuitry and pads of selective layers of the multilayer interconnection substrate, which also are typically formed of a copper material.
The term “through hole” or simply “hole” as used herein is meant to include both conductive and non-conductive apertures which may extend entirely through the multilayer interconnection substrate, or only partly there-through, including between two or more internal layers without being externally exposed. Such “through holes” or “holes” are often referred to as “vias” in the art and thus, the term “via” will be used hereafter in the present description.
In modern multilayer interconnection substrate technologies, a problem exists with the via structures in that there typically is an impedance mismatch between the transmission line and the via structure. Such mismatch occurs due to capacitive affects in the via structure, as described hereafter. Such impedance mismatch causes signals to not be propagated through the via structure correctly. There is greater signal reflection at portions of the via structure where there is greater impedance mismatch and less signal reflection at portions of the via structure where there is less impedance mismatch. Thus, it is important to match the impedance across the via structure as much as possible, i.e. within a tolerable error.
FIGS. 1A and 1B are exemplary cross-sectional diagrams of a known via arrangement in a multilayer interconnection substrate, e.g., printed circuit board, multilayer organic package, or multilayer ceramic package. In this via arrangement there is a significant amount of impedance mismatch, as discussed hereafter with regard to FIGS. 1A and 1B.
As shown in FIG. 1A, the multilayer interconnection substrate 100 includes a plurality of layers 110-170 and a via structure 180 that passes through each of the layers. The layer 140 is a core layer of the multilayer interconnection substrate 100 with layers 110-130 and 150-170 being build up layers. A ball grid array (BGA) pad 190 is provided on one external surface of the multilayer interconnection substrate 100.
As shown in FIG. 1A, the layers 110-130 are signal layers, or signal planes, in which signal transmission lines may be provided. Layers 150-170 are reference layers or reference planes that provide either voltage or ground connections. Typically, layers 150-170 alternate between voltage and ground reference planes. The via structure 180 comprises a plurality of microvias 182 provided at each layer and a plated through hole (PTH) 184. The microvia 182 are coupled to one another and to the PTH 184 to thereby provide a conductive pathway from one layer to another of the multilayer interconnection substrate 100. A signal transmission line 195 may be placed in contact with the via structure 180 to thereby permit passing of the signal from one layer of the multilayer interconnection substrate 100 to another or to an externally mounted integrated circuit device via BGA pad 190. The BGA pad is a necessarily large feature to accommodate a large solder ball that serves as the interconnect between the IC package and the next-level circuitry, typically a printed circuit board.
With reference now to FIG. 1B, a simplified cross section illustrating a conventional via structure is provided to illustrate the affects of the structure on via impedance. As shown in FIG. 1B, signal current is passed along the signal transmission line 195 and through the via structure 180 to the BGA pad 190. The via structure 180 has an inductance Lvia. In addition, the via structure 180 has a capacitance Cvia due to the overlap of the BGA pad 190 and one or more reference planes, e.g., voltage and/or ground layers or planes. The impedance of the via structure 180 may be calculated using the following relationship:Zvia=sqrt(Lvia/Cvia)where Zvia is the via structure 180 impedance, Lvia is the total inductance through the via structure 180, and Cvia is the total capacitance between the via structure 180 and a reference plane.
The value for Lvia is determined by the signal to ground via pitch. The value for Cvia is determined primarily by the overlap area between the BGA pad 190 and a reference plane. Cvia may be approximated using the following relationship:Cvia≈∈(S/d)
where ∈ is a dielectric constant, d is a dielectric thickness between the BGA pad 190 and the reference plane, and S is an overlap area between the BGA pad 190 and the reference plane.
The via structure 180 in FIGS. 1A and 1B has a significant mismatch of the impedance value for the via Zvia. For example, if a target impedance value is 100 ohms, this impedance may be achieved at the signal transmission line 195 since there is a minimal capacitive affect at this point in the via structure 180. However, at the BGA pad 190, due to the capacitive affect, i.e. Cvia, between the BGA pad 190 and the reference plane 170, using the equation for Zvia above, since the capacitance is greater at this point in the via structure 180, the impedance is significantly less. Thus, there is a mismatch in the impedance of the via structure 180 causing greater reflection at certain points of the structure than at other points.
It can be seen from the above that the via impedance Zvia may be controlled by controlling the amount of overlap of the BGA pad 190 and the reference plane, i.e. controlling the overlap area S and thus, the via capacitance Cvia. By decreasing the capacitance Cvia, the mismatch in the impedance Zvia is reduced.
In order to control the via impedance Zvia, and thereby reduce the mismatch in impedance, an alternative via structure has been developed that minimizes the overlap area between the BGA pad and the reference plane. FIG. 2 is an exemplary diagram illustrating this known alternative via structure. As shown in FIG. 2, the via structure is virtually identical to the structure shown in FIG. 1A with the exception that there is a large clearance hole provided between the reference planes 250-270, i.e. ground and voltage reference planes, and the BGA pad 290. As a result, there is no overlap between the BGA pad 290 and the reference plane 270 and hence, the via capacitance Cvia is reduced.
A problem exists in this alternative via structure, however, in that the structure becomes mechanically weak due to the large areas 202 and 205 of dielectric material where no metal material is provided. In the structure shown in FIG. 1A, because there is an overlap of metal structures, i.e. the BGA pad 190 and the metal reference layers 150-170, the structure is mechanically strong with regard to forces that may be exerted on the multilayer interconnection substrate 100, such as when placing external integrated circuit devices in contact with the BGA pad 190 and/or placing the multilayer interconnection substrate 100 on a printed circuit board. In addition, the structural stability at the BGA pad 190 is critical since most of the mechanical forces resulting from thermal cycling of the interconnect between the package and board ensue from the BGA ball located at this connection point. However, with the alternative structure shown in FIG. 2, the lack of metal in areas 202 and 205 makes the overall structure susceptible to fracture when a force is applied to the multilayer interconnection substrate 200.